-
公开(公告)号：US10896081B2
公开(公告)日：2021-01-19
申请号：US16219252
申请日：2018-12-13
摘要： A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
-
2.发明申请公开(公告)号：US20180089126A1
公开(公告)日：2018-03-29
申请号：US15278665
申请日：2016-09-28
发明人： David D. Cadigan , Samuel R. Connor , Michael A. Cracraft , William V. Huott , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
CPC分类号： G06F13/4022 , G06F1/3296 , G06F13/4286
摘要： An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
-
公开(公告)号：US09753806B1
公开(公告)日：2017-09-05
申请号：US15293645
申请日：2016-10-14
CPC分类号： G06F11/142 , G06F2201/805 , G11C11/401 , G11C29/028 , G11C29/4401 , G11C29/52 , G11C29/832 , G11C2029/0409
摘要： A method, system and memory controller are provided for implementing signal integrity fail recovery and mainline calibration for Dynamic Random Access Memory (DRAM). After identifying a failed DRAM, the DRAM is marked as bad and taken out of mainline operation. Characterization tests and periodic calibrations are run to evaluate optimal settings and to determine if the marked DRAM is recoverable. If recoverable, the marked DRAM chip is redeployed. If unrecoverable, error reporting is provided to the user.
-
公开(公告)号：US09418722B2
公开(公告)日：2016-08-16
申请号：US14878174
申请日：2015-10-08
IPC分类号： G11C11/406 , G11C7/24 , G11C11/4076 , G11C11/403
CPC分类号： G11C11/406 , G11C7/24 , G11C11/403 , G11C11/40603 , G11C11/4076
摘要： A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.
-
5.发明授权公开(公告)号：US09251054B2
公开(公告)日：2016-02-02
申请号：US14227187
申请日：2014-03-27
发明人： Edgar R. Cordero , Carlos A. Fernandez , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
CPC分类号： G06F12/0238 , G06F11/073 , G06F11/0793 , G06F11/1044 , G06F11/1048 , G06F11/108 , G06F2212/251
摘要： A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于利用双端口动态随机存取存储器（DRAM）配置来实现存储器子系统的增强的可靠性。 DRAM配置包括第一缓冲器和第二缓冲器，每个缓冲器包括有效性计数器。 接收缓冲器的有效性计数器随着来自传送缓冲器的每个相应数据行通过纠错码（ECC），可靠性，可用性和可服务性（RAS）逻辑被验证并递送到接收缓冲器而增加，而有效性计数器 传送缓冲区递减。 基于有效性计数器的相应计数值，从第一缓冲器或第二缓冲器读取或写入数据。
-
公开(公告)号：US20150228328A1
公开(公告)日：2015-08-13
申请号：US14694067
申请日：2015-04-23
IPC分类号： G11C11/4099 , G11C11/4076 , G11C11/4091 , G11C11/406
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4091 , G11C11/4099
摘要： A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.
摘要翻译： 公开了一种用于修改存储器件中的刷新之间的参考电压的方法和装置。 存储器阵列可以包括多个存储器单元。 存储器件还可以包括读出放大器。 读出放大器可以被配置为使用参考电压从多个存储单元读取数据。 存储器件还可以包括读出放大器参考电压修改电路。 感测放大器参考电压修改电路可以被配置为响应于检测到触发事件来检测触发事件并修改参考电压。
-
公开(公告)号：US20140317473A1
公开(公告)日：2014-10-23
申请号：US13867207
申请日：2013-04-22
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
IPC分类号： G11C29/08
CPC分类号： G11C29/4401 , G06F11/1048 , G11C29/42 , G11C29/702 , G11C2029/0411 , G11C2029/4402
摘要： A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在计算机系统中使用可重新配置的逻辑块实现ECC（纠错码）冗余。 当从存储器读取时检测到故障时，确定数据中的错误数据是否在数据或ECC组件中。 当在数据的ECC组件中找到不正确的数据，并且没有达到可操作的阈值时，采取预定的可靠性，可用性和可服务性（RAS）动作。 当在数据的ECC组件中识别出不正确的数据达到可操作的阈值时，执行分析处理以确定ECC逻辑是否有故障。 当检测到ECC逻辑中的故障时，所识别的ECC故障逻辑被替换为备用逻辑块。
-
公开(公告)号：US10268615B2
公开(公告)日：2019-04-23
申请号：US15683347
申请日：2017-08-22
IPC分类号： G06F13/38
摘要： A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.
-
公开(公告)号：US20180308545A1
公开(公告)日：2018-10-25
申请号：US15810290
申请日：2017-11-13
IPC分类号： G11C13/00 , G11C14/00 , G11C29/12 , G11C11/419
CPC分类号： G11C13/0069 , G11C7/12 , G11C11/412 , G11C11/4125 , G11C11/413 , G11C11/419 , G11C13/0004 , G11C14/0081 , G11C14/009 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/50012 , G11C2029/1204
摘要： Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
-
公开(公告)号：US20180308544A1
公开(公告)日：2018-10-25
申请号：US15496114
申请日：2017-04-25
IPC分类号： G11C13/00 , G11C11/419 , G11C29/12 , G11C14/00
CPC分类号： G11C13/0069 , G11C7/12 , G11C11/412 , G11C11/4125 , G11C11/413 , G11C11/419 , G11C13/0004 , G11C14/0081 , G11C14/009 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/50012 , G11C2029/1204
摘要： Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
-
-
-
-
-
-
-
-
-
搜索结果
60 条记录 (耗时 0.017 秒)
