A signal filter (100) comprises a first transferred impedance filter, TIF, (TIFA) having four differential signal paths (PA,1, PA,2, PA,3, PA,4) and a second TIF (TIFB) having four differential signal paths (PB,1, PB,2, PB,3, PB,4)−. A first differential signal port of the first TIF (32A) is coupled to a first differential signal port of the second TIF (32B). A first clock generator (12A) is arranged to provide first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (PA,1, PA,2, PA,3, PA,4), and a second clock generator (12B) is arranged to provide second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,J−, CLKB,Q−) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (PB,1, PB,2, PB,3, PB,4). The phases of the second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,Q−) are equal to the phases of the first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) delayed by 45 degrees. The first-TIF first, second, third and fourth clock signals (CLKA,I+, CLKA,Q+, CLKA,I−L, CLKAQ−) and the second-TIF first, second, third and fourth clock signals (CLKB,I+, CLKB,Q+, CLKB,I−, CLKB,Q−) have a duty cycle in the range 16.75% to 25%.