发明申请
US20150070368A1 Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource
审中-公开
指令集基于异构资源的基于架构的间隔符间通信
- 专利标题： Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource
- 专利标题（中）： 指令集基于异构资源的基于架构的间隔符间通信
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申请号： US14541933申请日： 2014-11-14
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公开(公告)号： US20150070368A1公开(公告)日： 2015-03-12
- 发明人: Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
- 申请人： Intel Corporation
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06T1/20
摘要：
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
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