公开(公告)号：US20240054595A1

公开(公告)日：2024-02-15

申请号：US17884755

申请日：2022-08-10

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Vasanth Ranganathan ,  James Valerio ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Ben J. Ashbaugh ,  Michal Mrozek ,  Murali Ramadoss ,  Hong Jiang ,  Ankur Shah

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06F9/3855

Abstract: Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.

公开(公告)号：US10863194B2

公开(公告)日：2020-12-08

申请号：US16552995

申请日：2019-08-27

Applicant: Intel Corporation

Inventor： Yi-Jen Chiu ,  Lidong Xu ,  Hong Jiang

IPC: H04N19/52 ,  H04N19/577 ,  H04N19/56 ,  H04N19/44 ,  H04N19/51

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

公开(公告)号：US10516898B2

公开(公告)日：2019-12-24

申请号：US15961677

申请日：2018-04-24

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Lidong Xu ,  Yu Han ,  Hong Jiang

IPC: H04N19/30 ,  H04N19/63 ,  H04N19/36 ,  H04N19/18 ,  H04N19/132 ,  H04N19/157

Abstract: Methods, systems, and computer program products for the generation of multiple layers of scaled encoded video data compatible with the HEVC standard. Residue from prediction processing may be transformed into coefficients in the frequency domain. The coefficients may then be sampled to create a layer of encoded data. The coefficients may be sampled in different ways to create multiple respective layers. The layers may then be multiplexed and sent to a decoder. There, one or more of the layers may be chosen. The choice of certain layer(s) may be dependent on the desired attributes of the resulting video. A certain level of video quality, frame rate, resolution, and/or bit depth may be desired, for example. The coefficients in the chosen layers may then be assembled to create a version of the residue to be used in video decoding.

公开(公告)号：US10123011B2

公开(公告)日：2018-11-06

申请号：US15589165

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Lidong Xu ,  Yi-Jen Chiu ,  Wenhao Zhang ,  Hong Jiang

IPC: H04N7/12 ,  H04N19/117 ,  H04N19/182 ,  H04N19/147 ,  H04N19/136

Abstract: Reconstructed picture quality for a video codec system may be improved by categorizing reconstructed pixels into different histogram bins with histogram segmentation and then applying different filters on different bins. Histogram segmentation may be performed by averagely dividing the histogram into M bins or adaptively dividing the histogram into N bins based on the histogram characteristics. Here M and N may be a predefined, fixed, non-negative integer value or an adaptively generated value at encoder side and may be sent to decoder through the coded bitstream.

公开(公告)号：US20180242012A1

公开(公告)日：2018-08-23

申请号：US15960120

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Yi-Jen Chiu ,  Lidong Xu ,  Hong Jiang

IPC: H04N19/52 ,  H04N19/577 ,  H04N19/56 ,  H04N19/51 ,  H04N19/44

CPC classification number: H04N19/52 ,  H04N19/44 ,  H04N19/51 ,  H04N19/56 ,  H04N19/577

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

公开(公告)号：US20170244963A1

公开(公告)日：2017-08-24

申请号：US15589165

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Lidong Xu ,  Yi-Jen Chiu ,  Wenhao Zhang ,  Hong Jiang

IPC: H04N19/117 ,  H04N19/147 ,  H04N19/182

CPC classification number: H04N19/117 ,  H04N19/136 ,  H04N19/147 ,  H04N19/182

Abstract: Reconstructed picture quality for a video codec system may be improved by categorizing reconstructed pixels into different histogram bins with histogram segmentation and then applying different filters on different bins. Histogram segmentation may be performed by averagely dividing the histogram into M bins or adaptively dividing the histogram into N bins based on the histogram characteristics. Here M and N may be a predefined, fixed, non-negative integer value or an adaptively generated value at encoder side and may be sent to decoder through the coded bitstream.

公开(公告)号：US09612833B2

公开(公告)日：2017-04-04

申请号：US14193550

申请日：2014-02-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Hong Jiang ,  James M. Holland

IPC: G06F12/08 ,  G06F9/312 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0842

CPC classification number: G06F9/30043 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/401 ,  Y02D10/13

Abstract: Technologies are presented that optimize data processing cost and efficiency. A computing system may comprise at least one processing element; a memory communicatively coupled to the at least one processing element; at least one compressor-decompressor communicatively coupled to the at least one processing element, and communicatively coupled to the memory through a memory interface; and a cache fabric comprising a plurality of distributed cache banks communicatively coupled to each other, to the at least one processing element, and to the at least one compressor-decompressor via a plurality of nodes. In this system, the at least one compressor-decompressor and the cache fabric are configured to manage and track uncompressed data of variable length for data requests by the processing element(s), allowing usage of compressed data in the memory.

公开(公告)号：US09582853B1

公开(公告)日：2017-02-28

申请号：US14816951

申请日：2015-08-03

Applicant: INTEL CORPORATION

Inventor： Jong Dae Oh ,  Vijay Sundaram ,  Yi-Jen Chiu ,  Hong Jiang

IPC: G06K9/00 ,  G06T3/40 ,  G06T7/00

CPC classification number: G06T3/4015 ,  G06T7/90 ,  G06T2207/10024

Abstract: Techniques related to demosaicing Bayer-type image data for image processing.

Abstract translation: 与去马赛克相关的技术用于图像处理的拜耳型图像数据。

公开(公告)号：US09510007B2

公开(公告)日：2016-11-29

申请号：US14691350

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： Hiu-Fai R. Chan ,  Scott W Cheng ,  Hong Jiang

IPC: G06F3/00 ,  H04N19/40 ,  G06F13/16 ,  G06F5/10 ,  H04N19/44 ,  H04N19/426

CPC classification number: H04N19/40 ,  G06F5/10 ,  G06F13/1673 ,  H04N19/426 ,  H04N19/44

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

公开(公告)号：US20150288977A1

公开(公告)日：2015-10-08

申请号：US14691350

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： Hiu-Fai R. Chan ,  Scott W. Cheng ,  Hong Jiang

IPC: H04N19/40 ,  H04N19/426

CPC classification number: H04N19/40 ,  G06F5/10 ,  G06F13/1673 ,  H04N19/426 ,  H04N19/44

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract translation: 描述了系统和方法，包括动态配置共享缓冲器以支持与不同视频编解码器格式相关联的至少两个视频读取流的处理。 方法可以包括：响应于与一个读取流相关联的存储器请求，确定共享缓冲器内的缓冲器写入地址，以及响应于与另一个读取流相关联的存储器请求，在共享缓冲器内确定不同的缓冲器写入地址。