Invention Application
US20150100761A1 SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
审中-公开
系统级芯片（SoC）执行位格式隔离指令
- Patent Title: SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
- Patent Title (中): 系统级芯片（SoC）执行位格式隔离指令
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Application No.: US14568754Application Date: 2014-12-12
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Publication No.: US20150100761A1Publication Date: 2015-04-09
- Inventor: Maxim Loktyukhin , Eric W Mahurin , Bret L Toll , Martin G Dixon , Sean P Mirkes , David L Kreitzer , ELMOUSTAPHA OULD-AHMED-VALL , Vinodh Gopal
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38
Abstract:
Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
Public/Granted literature
- US10579380B2 System-on-chip (SoC) to perform a bit range isolation instruction Public/Granted day:2020-03-03
Information query
