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    Processor to perform a bit range isolation instruction
    1.
    发明授权
    Processor to perform a bit range isolation instruction 有权

    公开(公告)号：US10579379B2

    公开(公告)日：2020-03-03

    申请号：US14568725

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Hand held device to perform a bit range isolation instruction
    2.
    发明授权
    Hand held device to perform a bit range isolation instruction 有权

    公开(公告)号：US10372455B2

    公开(公告)日：2019-08-06

    申请号：US14568812

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    System-on-chip (SoC) to perform a bit range isolation instruction
    3.
    发明授权
    System-on-chip (SoC) to perform a bit range isolation instruction 有权

    公开(公告)号：US10579380B2

    公开(公告)日：2020-03-03

    申请号：US14568754

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
    4.
    发明申请
    PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION 审中-公开
    处理器执行一个位格式隔离指令

    公开(公告)号：US20150100760A1

    公开(公告)日：2015-04-09

    申请号：US14568725

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  ELMOUSTAPHA OULD-AHMED-VALL ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Abstract translation: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

    Instruction execution that broadcasts and masks data values at different levels of granularity
    5.
    发明授权
    Instruction execution that broadcasts and masks data values at different levels of granularity 有权

    公开(公告)号：US12197617B2

    公开(公告)日：2025-01-14

    申请号：US18357066

    申请日：2023-07-21

    Applicant: Intel Corporation

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L Toll ,  Mark J. Charney

    IPC: G06F16/27 ,  G06F9/30 ,  G06F9/38 ,  G06F21/62 ,  G06F21/70

    Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.

    SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
    10.
    发明申请
    SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION 审中-公开
    系统级芯片（SoC）执行位格式隔离指令

    公开(公告)号：US20150100761A1

    公开(公告)日：2015-04-09

    申请号：US14568754

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  ELMOUSTAPHA OULD-AHMED-VALL ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Abstract translation: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

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