发明申请
- 专利标题： SELF-ALIGNMENT STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE
- 专利标题（中）： 自动对准结构，用于水平线芯片尺寸包装
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申请号： US14694780申请日： 2015-04-23
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公开(公告)号： US20150228599A1公开(公告)日： 2015-08-13
- 发明人: Yu-Chia LAI , Hsien-Ming TU , Tung-Liang SHAO , Hsien-Wei CHEN , Chang-Pin HUANG , Ching-Jung YANG
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 主分类号： H01L23/00
- IPC分类号： H01L23/00 ; H01L21/56
摘要：
A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
公开/授权文献
- US09318456B2 Self-alignment structure for wafer level chip scale package 公开/授权日：2016-04-19
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