公开(公告)号：US20210351130A1

公开(公告)日：2021-11-11

申请号：US17366575

申请日：2021-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20190131249A1

公开(公告)日：2019-05-02

申请号：US16231735

申请日：2018-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC分类号： H01L23/544 ,  H01L23/528 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

摘要： A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20160322238A1

公开(公告)日：2016-11-03

申请号：US14698694

申请日：2015-04-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsien-Wei CHEN ,  Jie CHEN

IPC分类号： H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L21/565 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/83005

摘要： A method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the substrate having the column structure such that the column structure is beneath the substrate; dipping the column structure of the flipped substrate into a molding material fluid contained in a container; and separating the column structure of the flipped substrate from the container to form a molding layer covering and in contact with the column structure.

摘要翻译： 形成模塑层的方法包括以下操作：在其上形成至少一个柱结构的基板; 翻转在具有柱结构的衬底上，使得柱结构在衬底下方; 将翻转的基板的柱结构浸入容纳在容器中的成型材料流体中; 并将翻转的基板的柱结构与容器分离以形成覆盖并与柱结构接触的成型层。

公开(公告)号：US20140106544A1

公开(公告)日：2014-04-17

申请号：US14132192

申请日：2013-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsien-Wei CHEN ,  Shih-Hsun HSU

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  B28D5/022 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

摘要翻译： 具有辅助切割结构的半导体晶片。 晶片包括具有前表面和后表面的基板。 衬底的前表面包括由至少一个切割通道分开的至少两个器件区域。 衬底的后表面包括形成在其中并与切割通道基本对齐的至少一个预切割沟槽。 还公开了一种用于切割半导体晶片的方法。

公开(公告)号：US20240079324A1

公开(公告)日：2024-03-07

申请号：US18503947

申请日：2023-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Chen-Hua YU ,  Der-Chyang YEH ,  Hsien-Wei CHEN

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20180294227A1

公开(公告)日：2018-10-11

申请号：US16004573

申请日：2018-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Hsien-Wei CHEN

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5386 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/46 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/4807 ,  H01L2224/4846

摘要： Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via. The second surface is opposite to the first surface. A portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

公开(公告)号：US20150228599A1

公开(公告)日：2015-08-13

申请号：US14694780

申请日：2015-04-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chia LAI ,  Hsien-Ming TU ,  Tung-Liang SHAO ,  Hsien-Wei CHEN ,  Chang-Pin HUANG ,  Ching-Jung YANG

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/10125 ,  H01L2224/11015 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

摘要翻译： 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。

公开(公告)号：US20150021759A1

公开(公告)日：2015-01-22

申请号：US13943284

申请日：2013-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsien-Wei CHEN

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14164 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/1713 ,  H01L2224/17135 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01011 ,  H01L2924/01079 ,  H01L2924/00012

摘要： Embodiments of mechanisms for forming a package structure are provided. A method for forming a package structure includes providing a semiconductor die and forming a first bump structure and a second bump structure over the semiconductor die. The second bump structure is thinner and wider than the first bump structure.The method also includes providing a substrate having a first contact pad and a second contact pad formed on the substrate. The method further includes forming a first solder paste structure and a second solder paste structure over the first contact pad and the second contact pad, respectively. The second solder paste structure is thicker than the first solder paste structure. In addition, the method includes reflowing the first bump structure and the second bump structure with the first solder paste structure and the second solder paste structure, respectively, to bond the semiconductor die to the substrate.

摘要翻译： 提供了用于形成封装结构的机构的实施例。 一种用于形成封装结构的方法包括提供半导体管芯并在半导体管芯上方形成第一凸块结构和第二凸块结构。 第二凸块结构比第一凸块结构更薄和更宽。 该方法还包括提供具有第一接触焊盘和形成在基板上的第二接触焊盘的衬底。 该方法还包括分别在第一接触焊盘和第二接触焊盘上形成第一焊膏结构和第二焊膏结构。 第二焊膏结构比第一焊膏结构厚。 此外，该方法包括分别用第一焊膏结构和第二焊膏结构回流第一凸块结构和第二凸块结构，以将半导体管芯接合到衬底。

公开(公告)号：US20200286830A1

公开(公告)日：2020-09-10

申请号：US16883210

申请日：2020-05-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20200058620A1

公开(公告)日：2020-02-20

申请号：US16663064

申请日：2019-10-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Hsien-Wei CHEN

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

摘要： A chip package is provided. The chip package includes a semiconductor die and a protective layer surrounding the semiconductor die. The chip package also includes an interface between the semiconductor die and the protective layer. The chip package further includes a conductive line over the protective layer and the semiconductor die. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the interface. In a top view of the conductive layer, line widths of the first portion and the second portion are different from each other.