Invention Application
- Patent Title: CORELESS PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF
- Patent Title (中): 无缝包装基板及其制造方法
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Application No.: US14583317Application Date: 2014-12-26
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Publication No.: US20160021743A1Publication Date: 2016-01-21
- Inventor: Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
- Applicant: Siliconware Precision Industries Co., Ltd.
- Priority: TW103124499 20140717
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K3/46 ; H05K3/40 ; H05K1/02 ; H05K3/02

Abstract:
A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
Public/Granted literature
- US09510463B2 Coreless packaging substrate and fabrication method thereof Public/Granted day:2016-11-29
Information query