发明申请
- 专利标题： BACKSIDE THROUGH SILICON VIAS AND MICRO-CHANNELS IN THREE DIMENSIONAL INTEGRATION
- 专利标题（中）： 通过硅三维和微通道的三维集成
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申请号： US14450203申请日： 2014-08-01
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公开(公告)号： US20160035704A1公开(公告)日： 2016-02-04
- 发明人: Zhijiong Luo
- 申请人： Empire Technology Development LLC
- 主分类号： H01L25/065
- IPC分类号： H01L25/065 ; H01L23/48 ; H01L21/67 ; H01L21/768 ; H01L21/3065 ; H01L21/285 ; H01L25/00 ; H01L23/532
摘要：
Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.
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