Invention Application
US20160064228A1 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR 有权
形成包括微​​电子晶体的微电子材料和半导体结构的半导体结构的方法

  • Patent Title: METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR
  • Patent Title (中): 形成包括微​​电子晶体的微电子材料和半导体结构的半导体结构的方法
  • Application No.: US14471812
    Application Date: 2014-08-28
  • Publication No.: US20160064228A1
    Publication Date: 2016-03-03
  • Inventor: Ralf van BentumGunter Grasshoff
  • Applicant: GLOBALFOUNDRIES Inc.
  • Main IPC: H01L21/28
  • IPC: H01L21/28 H01L29/51 H01L21/8234 H01L27/22
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR
Abstract:
An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.
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