Invention Application
US20160064328A1 MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING 审中-公开
多芯硅基板 - 不包括芯片包装

MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING
Abstract:
Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.
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