Invention Application
- Patent Title: MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING
- Patent Title (中): 多芯硅基板 - 不包括芯片包装
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Application No.: US14469500Application Date: 2014-08-26
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Publication No.: US20160064328A1Publication Date: 2016-03-03
- Inventor: Woon-Seong Kwon , Suresh Ramalingam
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/07 ; H01L25/00 ; H01L23/00

Abstract:
Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.
Public/Granted literature
- US10468351B2 Multi-chip silicon substrate-less chip packaging Public/Granted day:2019-11-05
Information query
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