Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.