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公开(公告)号：US09859877B2
公开(公告)日：2018-01-02
申请号：US15072613
申请日：2016-03-17
Applicant: SK hynix Inc.
Inventor： Jae Hoon Jung
Abstract: A signal processing circuit may be provided. The signal processing circuit may include a mask generation circuit configured to output a mask signal in response to an internal control signal and masking information; and a masking circuit configured to mask the internal control signal in response to the mask signal, and output a masked control signal, wherein the mask generation circuit resets the mask signal in response to an internal reset signal, regardless of a pause polarity of the internal control signal.
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2.发明申请公开(公告)号：US20160291068A1
公开(公告)日：2016-10-06
申请号：US14933542
申请日：2015-11-05
Applicant: MEDIATEK INC.
Inventor： Huajun Wen , Hugh Thomas Mair , Hsin-Chen Chen , Brian King Flachs
CPC classification number: G06F1/3203 , G06F1/04
Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
Abstract translation: 动态功率计电路接收一组时钟信号。 时钟信号由时钟和加法器相加，从而产生时钟和值。 至少部分地基于时钟和值产生动态功率计输出值。 在一个具体示例中，动态功率计电路接收时钟信号，并从中产生时钟和模型子值。 动态功率计电路还接收事件信号，并从它们生成建筑事件模型子值。 然后将对应的一对时钟和模型子值和架构事件模型子值进行比例组合，从而生成动态功率计输出值。 由于使用了事件信号和时钟信号两者，所以产生动态功率计输出值流，其更紧密地跟踪被监控电路的实际动态功率。
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公开(公告)号：US3857101A
公开(公告)日：1974-12-24
申请号：US36551373
申请日：1973-05-31
Applicant: GEN ELECTRIC
Inventor： PUCKETTE C , BUTLER W
Abstract: A multi-state switch connected to DATA inputs of a counter, and NAND logic circuitry interconnected with the counter CLOCK and CLEAR inputs and CARRY output determine the number of clock pulses developed for a burst thereof occurring during the period of a lower repetition rate pulse signal applied to the counter and NAND circuit.
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公开(公告)号：US3745380A
公开(公告)日：1973-07-10
申请号：US3745380D
申请日：1971-09-16
Applicant: KITAJIMA K , MITSUI M , NAGANO A , NAKAKOUJI S
Inventor： MITSUI M , NAKAKOUJI S , KITAJIMA K , NAGANO A
Abstract: A timing pulse generator, which produces a plurality of timing pulses, is controlled by a series connected arrangement of a monostable-multivibrator and a clock pulse generator. The monostable multivibrator or delay is triggered by an output from the timing pulse generator, so as to render the clock pulse generator disabled for a predetermined period of time, whereby both clock pulses and timing pulses will be inhibited for the predetermined period of time.
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公开(公告)号：US3566149A
公开(公告)日：1971-02-23
申请号：US3566149D
申请日：1969-06-25
Applicant: LORAIN PROD CORP
Inventor： PARADISSIS PANTELIS P
Abstract: A control circuit for supplying a modulated train of short duration firing pulses to each of a plurality of thyristors. A pulse suppression circuit is connected to a plurality of oscillator circuits which supply firing pulses to respective thyristors. The pulse suppression circuit disables the output of all oscillator circuits to prevent simultaneous firing of the different thyristors only during starting and only during the period preceeding the firing of each thyristor.
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Patent Agency Ranking
公开(公告)号：US20170366174A1
公开(公告)日：2017-12-21
申请号：US15693440
申请日：2017-08-31
Applicant: Altera Corporation
Inventor： Nelson Gaspard , Yanzhong Xu
Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.
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公开(公告)号：US20160065190A1
公开(公告)日：2016-03-03
申请号：US14823647
申请日：2015-08-11
Applicant: MARVELL WORLD TRADE LTD
Inventor： Gideon PAUL
CPC classification number: H03K3/012 , H03K3/356121 , H03K3/35625 , H03K3/66 , H03K5/24
Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.
Abstract translation: 本公开的方面提供了一种数据存储电路。 数据存储电路包括第一锁存器，第二锁存器和时钟门控和缓冲器电路。 第一锁存器被配置为当时钟信号处于第一状态时响应于数据输入向第二锁存器提供中间输出，并且当时钟信号处于第二状态时保持中间输出，并且第二锁存器是 被配置为响应于中间输出和时钟信号提供数据输出。 时钟门控和缓冲电路被配置为提供时钟信号，并且当中间输出保持不变时，抑制将时钟信号提供给第一锁存器和第二锁存器中的一个或两个。
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公开(公告)号：US09106216B1
公开(公告)日：2015-08-11
申请号：US14448593
申请日：2014-07-31
Applicant: Microsoft Corporation
Inventor： Avdhesh Chhodavdia , Michael S. Fenton , Sheethal Somesh Nayak
Abstract: An electronic device includes a configurable pulse generator configured to generate a programmable master pulse train. One or more functional circuits of the electronic device includes a programming interface to receive one or more a programmable slave pulse parameters for the one or more functional circuits. The programmable slave pulse parameters are dependent upon the programmable master pulse train. A slave pulse generator generates a slave pulse for one of the functional circuits based on the one or more programmable slave pulse parameters corresponding to the functional circuits relative to the programmable master pulse train.
Abstract translation: 电子设备包括被配置为产生可编程主脉冲串的可配置脉冲发生器。 电子设备的一个或多个功能电路包括用于接收一个或多个功能电路的一个或多个可编程从属脉冲参数的编程接口。 可编程从属脉冲参数取决于可编程主脉冲串。 从脉冲发生器基于与功能电路相对于可编程主脉冲串相对应的一个或多个可编程从属脉冲参数，产生功能电路之一的从脉冲。
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公开(公告)号：US5540682A
公开(公告)日：1996-07-30
申请号：US372368
申请日：1995-01-13
Applicant: John A. Gardner , Geoffrey P. Taylor , Kevin A. Hebborn , Razi Adelinia
Inventor： John A. Gardner , Geoffrey P. Taylor , Kevin A. Hebborn , Razi Adelinia
CPC classification number: G06F1/025 , A61B18/1206 , H03K3/66 , H03K3/72 , H03K3/78 , A61B2017/00154 , A61B2017/00172 , A61B2017/0019
Abstract: Electrosurgery apparatus has a processor that generates a data stream output representing the characteristics of the electrosurgery pulses to be generated. The data stream output comprises digitally-represented values indicative respectively of the width of each pulse, the duration of a first period during which pulses are to be generated, the duration of a second period during which pulses are not to be generated, the duration of a third period during which pulses are to be generated and the duration of a fourth period during which pulses are not to be generated. The data stream also includes digital instructions as to whether or not the electrosurgery output is to be cut only and whether it is to include spray coagulation. Three switch control units receive the data stream and provide outputs to three switching circuits, which provide two monopolar and one bipolar output. Each switching circuit includes a transformer connected to receive the outputs from the switch control units.
Abstract translation: 电外科设备具有产生表示要产生的电外科脉冲的特性的数据流输出的处理器。 数据流输出包括分别指示每个脉冲的宽度，要产生脉冲的第一周期的持续时间，不产生脉冲的第二周期的持续时间的数字表示的值， 将产生脉冲的第三周期和不产生脉冲的第四周期的持续时间。 数据流还包括关于电外科输出是否仅被切割以及是否包括喷雾凝结的数字指令。 三个开关控制单元接收数据流，并向三个开关电路提供输出，这三个开关电路提供两个单极和一个双极输出。 每个开关电路包括连接以接收来自开关控制单元的输出的变压器。
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公开(公告)号：US4761567A
公开(公告)日：1988-08-02
申请号：US52623
申请日：1987-05-20
Applicant: Donald M. Walters, Jr. , Gigy Baror
Inventor： Donald M. Walters, Jr. , Gigy Baror
IPC: G11C11/407 , G06F1/04 , G06F1/06 , G06F1/10 , H03K5/00 , H03K19/096 , H03K3/66 , H03K5/15
CPC classification number: G06F1/06
Abstract: An integrated circuit includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS level phase clock signals for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.
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