Invention Application
US20160085900A1 Activity-Driven Capacitance Reduction to Reduce Dynamic Power Consumption in an Integrated Circuit 有权
活动驱动的电容降低以降低集成电路中的动态功耗

Activity-Driven Capacitance Reduction to Reduce Dynamic Power Consumption in an Integrated Circuit
Abstract:
In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.
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