公开(公告)号：US20160085900A1

公开(公告)日：2016-03-24

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。

公开(公告)号：US09292648B1

公开(公告)日：2016-03-22

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。