Invention Application
US20160097898A1 PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE
审中-公开
用于制造包含至少一个共振波导的集成电路的方法
- Patent Title: PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE
- Patent Title (中): 用于制造包含至少一个共振波导的集成电路的方法
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Application No.: US14970792Application Date: 2015-12-16
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Publication No.: US20160097898A1Publication Date: 2016-04-07
- Inventor: Sylvain Joblot , Pierre Bar
- Applicant: STMicroelectronics SA
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Priority: FR1154824 20110601
- Main IPC: G02B6/12
- IPC: G02B6/12 ; H01L21/48 ; H01L21/768
Abstract:
An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
Public/Granted literature
- US09673088B2 Process for fabricating an integrated circuit comprising at least one coplanar waveguide Public/Granted day:2017-06-06
Information query
