公开(公告)号：US09418954B2

公开(公告)日：2016-08-16

申请号：US14659680

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/3213 ,  H01L21/56 ,  H01L21/768 ,  H01L23/36 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。

公开(公告)号：US09165861B2

公开(公告)日：2015-10-20

申请号：US14287343

申请日：2014-05-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Simon Gousseau ,  Yann Beilliard

IPC: H01L23/427 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.

Abstract translation: 用于在衬底内部生产至少一个穿硅的方法可包括在衬底的第一侧从衬底的第一侧形成空腔，直到导电部分出现。 该方法还可以包括在空腔的底部和壁上形成导电层，并且至少部分地在空腔外部的第一侧上形成导电层。 该方法还可以包括用至少一种相变材料至少部分地填充空腔。 另一方面涉及三维综合结构。

公开(公告)号：US09673088B2

公开(公告)日：2017-06-06

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  G02B6/12 ,  H01P11/00 ,  H01L21/762 ,  H01L21/48

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US20160322276A1

公开(公告)日：2016-11-03

申请号：US15204488

申请日：2016-07-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

公开(公告)号：US20160204031A1

公开(公告)日：2016-07-14

申请号：US15074130

申请日：2016-03-18

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

公开(公告)号：US20160197048A1

公开(公告)日：2016-07-07

申请号：US15070046

申请日：2016-03-15

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-Francois Carpentier

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H04B1/3827 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01Q13/10 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive connection, and an integrated circuit arranged between the support element and the interface device and connected to the interface device by a second electrically conductive connection. A filler region is positioned between the second electrically conductive connection and between the interface device and the integrated circuit. An antenna is distributed over the interface device and the integrated circuit and has a radiating element electromagnetically coupled with an excitation element through the interconnection of a slot.

Abstract translation: 三维集成结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，以及布置在支撑元件和接口装置之间并且通过第二导电连接到接口装置的集成电路 连接。 填充区域位于第二导电连接之间以及接口装置和集成电路之间。 天线分布在接口装置和集成电路上，并且具有通过插槽的互连与激励元件电磁耦合的辐射元件。

公开(公告)号：US20140075726A1

公开(公告)日：2014-03-20

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。

公开(公告)号：US09647625B2

公开(公告)日：2017-05-09

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02 ,  H03H9/02 ,  H03H3/04 ,  H03H9/00 ,  H03H9/17 ,  G02F1/1337 ,  G01N29/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

公开(公告)号：US20150270192A1

公开(公告)日：2015-09-24

申请号：US14659680

申请日：2015-03-17

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L21/3213 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。

公开(公告)号：US09818646B2

公开(公告)日：2017-11-14

申请号：US15583342

申请日：2017-05-01

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: G02B6/12 ,  H01L21/768 ,  H01L21/48 ,  H01L21/762 ,  H01L23/66 ,  H01P11/00

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.