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公开(公告)号：US09728337B2
公开(公告)日：2017-08-08
申请号：US14416978
申请日：2013-07-12
Inventor： Yann Lamy , Olivier Guiller , Sylvain Joblot
Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
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公开(公告)号：US09647625B2
公开(公告)日：2017-05-09
申请号：US14084394
申请日：2013-11-19
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： David Petit , Sylvain Joblot , Pierre Bar , Jean-Francois Carpentier , Pierre Dautriche
CPC classification number: H03H3/02 , G01N29/022 , G02F1/133707 , H03H3/04 , H03H9/0028 , H03H9/02102 , H03H9/175 , Y10T29/42 , Y10T29/49005 , Y10T29/49155
Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.
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公开(公告)号：US09673088B2
公开(公告)日：2017-06-06
申请号：US14970792
申请日：2015-12-16
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L21/768 , G02B6/12 , H01P11/00 , H01L21/762 , H01L21/48
CPC classification number: H01L21/76831 , G02B6/12 , H01L21/4846 , H01L21/76224 , H01L21/76898 , H01L23/66 , H01P11/003
Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
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公开(公告)号：US20160204031A1
公开(公告)日：2016-07-14
申请号：US15074130
申请日：2016-03-18
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L21/768 , H01L23/528 , H01L23/532 , H01L23/66
CPC classification number: H01L21/76898 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/528 , H01L23/53228 , H01L23/5329 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2924/0002 , H01P3/003 , H01P3/006 , H01P11/003 , H01L2924/00
Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.
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公开(公告)号：US20150206662A1
公开(公告)日：2015-07-23
申请号：US14416978
申请日：2013-07-12
Inventor： Yann Lamy , Olivier Guiller , Sylvain Joblot
Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
Abstract translation: 一种用于在基板的一部分中制造电容器堆叠的方法，所述方法包括：从所述基板的上表面沿着所述基板的所述部分的厚度形成空腔，将有助于所述电容器堆叠的多个层沉积到所述基板上 空腔的壁和上表面上，并且从层中去除物质直到达到上表面的表面。 腔的形成包括形成至少一个沟槽，并且与每个沟槽相关联，至少一个盒子。 至少一个沟槽包括通向盒子的沟槽出口。 盒子包括在上表面开口的盒子出口，盒子出口的形状大于沟槽出口。
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Patent Agency Ranking
公开(公告)号：US20140075726A1
公开(公告)日：2014-03-20
申请号：US14084394
申请日：2013-11-19
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： David Petit , Sylvain Joblot , Pierre Bar , Jean-Francois Carpentier , Pierre Dautriche
IPC: H03H3/02
CPC classification number: H03H3/02 , G01N29/022 , G02F1/133707 , H03H3/04 , H03H9/0028 , H03H9/02102 , H03H9/175 , Y10T29/42 , Y10T29/49005 , Y10T29/49155
Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.
Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。
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公开(公告)号：US09455191B2
公开(公告)日：2016-09-27
申请号：US15074130
申请日：2016-03-18
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L21/44 , H01L21/311 , H01L21/768 , H01L23/66 , H01L23/528 , H01L23/532
CPC classification number: H01L21/76898 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/528 , H01L23/53228 , H01L23/5329 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2924/0002 , H01P3/003 , H01P3/006 , H01P11/003 , H01L2924/00
Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.
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公开(公告)号：US08994172B2
公开(公告)日：2015-03-31
申请号：US13873103
申请日：2013-04-29
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L23/48 , H01L23/28 , H01L21/768 , H01L23/538 , H01L23/14 , H01L23/498 , H01L21/48
CPC classification number: H01L23/28 , H01L21/486 , H01L21/76877 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/5384 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
Abstract: A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.
Abstract translation: 具有通孔的芯片，其中通孔由具有绝缘壁的开口形成，绝缘壁涂覆有导电材料，并且填充有易变形的绝缘材料，与另一芯片的连接元件布置在容易变形的绝缘材料的前面。
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公开(公告)号：US20130292824A1
公开(公告)日：2013-11-07
申请号：US13873103
申请日：2013-04-29
Applicant: STMICROELECTRONICS SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L23/28 , H01L23/538 , H01L21/768
CPC classification number: H01L23/28 , H01L21/486 , H01L21/76877 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/5384 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
Abstract: A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.
Abstract translation: 具有通孔的芯片，其中通孔由具有绝缘壁的开口形成，绝缘壁涂覆有导电材料，并且填充有易变形的绝缘材料，与另一芯片的连接元件布置在容易变形的绝缘材料的前面。
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10.发明授权公开(公告)号：US09818646B2
公开(公告)日：2017-11-14
申请号：US15583342
申请日：2017-05-01
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: G02B6/12 , H01L21/768 , H01L21/48 , H01L21/762 , H01L23/66 , H01P11/00
CPC classification number: H01L21/76831 , G02B6/12 , H01L21/4846 , H01L21/76224 , H01L21/76898 , H01L23/66 , H01P11/003
Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
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