Invention Application
US20160124883A1 Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System
有权
具有非阻塞性高性能交易信用系统的多核总线架构
- Patent Title: Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System
- Patent Title (中): 具有非阻塞性高性能交易信用系统的多核总线架构
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Application No.: US14530203Application Date: 2014-10-31
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Publication No.: US20160124883A1Publication Date: 2016-05-05
- Inventor: David M. Thompson , Timothy Anderson , Joseph Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
- Applicant: Texas Instruments Incorporated
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42 ; G06F13/364

Abstract:
This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
Public/Granted literature
- US09904645B2 Multicore bus architecture with non-blocking high performance transaction credit system Public/Granted day:2018-02-27
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