Invention Application
US20160126108A1 METHOD OF REDUCING GATE LEAKAGE IN A MOS DEVICE BY IMPLANTING GATE LEAKAGE REDUCING SPECIES INTO THE EDGE OF THE GATE
审中-公开
通过将栅栏减少物种植入栅格边缘减少MOS器件中的栅极泄漏的方法
- Patent Title: METHOD OF REDUCING GATE LEAKAGE IN A MOS DEVICE BY IMPLANTING GATE LEAKAGE REDUCING SPECIES INTO THE EDGE OF THE GATE
- Patent Title (中): 通过将栅栏减少物种植入栅格边缘减少MOS器件中的栅极泄漏的方法
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Application No.: US14531308Application Date: 2014-11-03
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Publication No.: US20160126108A1Publication Date: 2016-05-05
- Inventor: Ebenezer Eshun
- Applicant: Texas Instruments Incorporated
- Main IPC: H01L21/3115
- IPC: H01L21/3115 ; H01L29/51 ; H01L21/28 ; H01L21/265
Abstract:
In a MOS device, gate leakage is reduced by implanting gate oxide leakage reduction species such as nitrogen into the gate oxide along the edges of the gate to reduce gate leakage and hence reduce data retention fails in SRAM devices and allow low Vdd SRAM operation without increasing gate oxide thickness. By implanting nitrogen along the edges of the gate it simultaneously replaces lost gate oxide nitrogen to further reduce gate leakage.
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