Invention Application
- Patent Title: STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT
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Application No.: US14933226Application Date: 2015-11-05
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Publication No.: US20160126311A1Publication Date: 2016-05-05
- Inventor: Fatma Arzum Simsek-Ege , Jie Jason Sun , Benben Li , Srikant Jayanti , Han Zhao , Guangyu Huang , Haitao Liu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L27/115
Abstract:
A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
Public/Granted literature
- US09412821B2 Stacked thin channels for boost and leakage improvement Public/Granted day:2016-08-09
Information query
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