公开(公告)号：US09209199B2

公开(公告)日：2015-12-08

申请号：US14222070

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Fatma Arzum Simsek-Ege ,  Jie Jason Sun ,  Benben Li ,  Srikant Jayanti ,  Han Zhao ,  Guangyu Huang ,  Haitao Liu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16

Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.

Abstract translation: 中空通道存储器件包括源极层，形成在源极层上的第一中空沟槽柱结构以及形成在第一中空通道柱结构上的第二中空沟槽柱结构。 第一中空通道柱结构包括第一细通道，第二中空通道柱结构包括与第一薄通道接触的第二细通道。 在一个示例性实施例中，第一薄沟道包括第一级掺杂; 并且第二薄沟道包括与第一掺杂水平不同的第二掺杂水平。 在另一示例性实施例中，第一和第二级掺杂是相同的。

公开(公告)号：US20160126311A1

公开(公告)日：2016-05-05

申请号：US14933226

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Fatma Arzum Simsek-Ege ,  Jie Jason Sun ,  Benben Li ,  Srikant Jayanti ,  Han Zhao ,  Guangyu Huang ,  Haitao Liu

IPC: H01L29/10 ,  H01L27/115

CPC classification number: H01L29/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16

Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.

公开(公告)号：US09412821B2

公开(公告)日：2016-08-09

申请号：US14933226

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Fatma Arzum Simsek-Ege ,  Jie Jason Sun ,  Benben Li ,  Srikant Jayanti ,  Han Zhao ,  Guangyu Huang ,  Haitao Liu

IPC: H01L27/115 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16

Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.