Invention Application
- Patent Title: METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS
- Patent Title (中): 方法和结构与指导VIAS接触导电层
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Application No.: US14905269Application Date: 2013-08-21
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Publication No.: US20160148869A1Publication Date: 2016-05-26
- Inventor: Richard E. SCHENKER , Elliot N. TAN
- Applicant: INTEL CORPORATION
- International Application: PCT/US2013/056039 WO 20130821
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/02 ; H01L21/768 ; H01L21/033 ; H01L21/311 ; H01L23/528

Abstract:
An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.
Public/Granted literature
- US09659860B2 Method and structure to contact tight pitch conductive layers with guided vias Public/Granted day:2017-05-23
Information query
IPC分类: