Invention Application
- Patent Title: DIGITAL PHASE-LOCKED LOOP AND METHOD OF OPERATING THE SAME
- Patent Title (中): 数字锁相环及其操作方法
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Application No.: US14955802Application Date: 2015-12-01
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Publication No.: US20160164527A1Publication Date: 2016-06-09
- Inventor: Min-young SONG , Tae-ik KIM , Ji-hyun KIM
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Priority: KR10-2014-0172388 20141203
- Main IPC: H03L7/081
- IPC: H03L7/081 ; H03L7/095 ; H03L7/08 ; H03L7/099

Abstract:
Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.
Public/Granted literature
- US09564908B2 Digital phase-locked loop and method of operating the same Public/Granted day:2017-02-07
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