Invention Application
- Patent Title: INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING
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Application No.: US14568312Application Date: 2014-12-12
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Publication No.: US20160169967A1Publication Date: 2016-06-16
- Inventor: Steven M. Douskey , Michael J. Hamilton , Amanda R. Kaufer
- Applicant: International Business Machines Corporation
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317

Abstract:
A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.
Public/Granted literature
- US09551747B2 Inserting bypass structures at tap points to reduce latch dependency during scan testing Public/Granted day:2017-01-24
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