Invention Application
US20160182259A1 WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY
有权
具有协调时序恢复的线路接收器电路
- Patent Title: WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY
- Patent Title (中): 具有协调时序恢复的线路接收器电路
-
Application No.: US14573343Application Date: 2014-12-17
-
Publication No.: US20160182259A1Publication Date: 2016-06-23
- Inventor: Tawfiq Musah , Gokce Keskin , Ganesh Balamurugan , James E. Jaussi , Bryan K. Casper
- Applicant: Intel Corporation
- Main IPC: H04L25/03
- IPC: H04L25/03 ; H04L7/02

Abstract:
Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
Public/Granted literature
- US09374250B1 Wireline receiver circuitry having collaborative timing recovery Public/Granted day:2016-06-21
Information query