Invention Application
US20160245861A1 METHODS AND DEVICES FOR DETERMINING LOGICAL TO PHYSICAL MAPPING ON AN INTEGRATED CIRCUIT
审中-公开
用于确定在集成电路上进行逻辑映射的方法和装置
- Patent Title: METHODS AND DEVICES FOR DETERMINING LOGICAL TO PHYSICAL MAPPING ON AN INTEGRATED CIRCUIT
- Patent Title (中): 用于确定在集成电路上进行逻辑映射的方法和装置
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Application No.: US15058263Application Date: 2016-03-02
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Publication No.: US20160245861A1Publication Date: 2016-08-25
- Inventor: Stanton Petree Ashburn , Daniel L. Corum, JR. , Abha Singh Kasper , Harold C. Waite , Eric D. Rullan , Donald L. Plumton , Douglas A. Prinslow
- Applicant: Texas Instruments Incorporated
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177 ; H01L27/02 ; G01R31/28
Abstract:
Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.
Information query
