公开(公告)号：US20160245861A1

公开(公告)日：2016-08-25

申请号：US15058263

申请日：2016-03-02

Applicant: Texas Instruments Incorporated

Inventor： Stanton Petree Ashburn ,  Daniel L. Corum, JR. ,  Abha Singh Kasper ,  Harold C. Waite ,  Eric D. Rullan ,  Donald L. Plumton ,  Douglas A. Prinslow

IPC: G01R31/317 ,  G01R31/3177 ,  H01L27/02 ,  G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/2894 ,  G01R31/3177 ,  G11C29/56008 ,  G11C2029/1806 ,  G11C2029/5604 ,  H01L27/0207

Abstract: Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.

Abstract translation: 本文公开了用于将逻辑地址映射到集成电路管芯上的物理位置的设备。 实施例包括具有可通过逻辑地址电可访问的多个位的管芯。 多个位有意引起形成预定故障模式的缺陷。