Invention Application
US20160245898A1 Systems and Methods for Cascading Radar Chips Having a Low Leakage Buffer
有权
具有低泄漏缓冲器的级联雷达芯片的系统和方法
- Patent Title: Systems and Methods for Cascading Radar Chips Having a Low Leakage Buffer
- Patent Title (中): 具有低泄漏缓冲器的级联雷达芯片的系统和方法
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Application No.: US14630754Application Date: 2015-02-25
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Publication No.: US20160245898A1Publication Date: 2016-08-25
- Inventor: Hao Li , Herbert Knapp
- Applicant: Infineon Technologies AG
- Main IPC: G01S7/03
- IPC: G01S7/03
Abstract:
A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.
Public/Granted literature
- US09910133B2 Systems and methods for cascading radar chips having a low leakage buffer Public/Granted day:2018-03-06
Information query
