Systems and methods for cascading radar chips having a low leakage buffer

    公开(公告)号:US09910133B2

    公开(公告)日:2018-03-06

    申请号:US14630754

    申请日:2015-02-25

    CPC classification number: G01S7/032 G01S13/931

    Abstract: A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

    Power sensor for integrated circuits

    公开(公告)号:US10466339B2

    公开(公告)日:2019-11-05

    申请号:US16186938

    申请日:2018-11-12

    Abstract: An on-chip power sensor and a millimeter-wave communication device (e.g. transmitter or transceiver) on a chip including the on-chip power sensor are described. The millimeter-wave communication device can also include a coupler disposed on a transmit path, the coupler being configured to receive a transmit signal and to provide the transmit signal to an antenna connection (e.g. pad). The on-chip power sensor can be configured to receive a coupled portion of the transmit signal from the coupler, and measure a transmit power of the transmit signal based on the coupled portion of the transmit signal.

    SYSTEMS AND METHODS FOR CASCADING RADAR CHIPS HAVING A LOW LEAKAGE BUFFER

    公开(公告)号:US20180156890A1

    公开(公告)日:2018-06-07

    申请号:US15887030

    申请日:2018-02-02

    CPC classification number: G01S7/032 G01S13/931

    Abstract: A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

    RF FRONT-END WITH POWER SENSOR CALIBRATION
    6.
    发明申请
    RF FRONT-END WITH POWER SENSOR CALIBRATION 审中-公开
    RF前端带功率传感器校准

    公开(公告)号:US20160329972A1

    公开(公告)日:2016-11-10

    申请号:US15145485

    申请日:2016-05-03

    CPC classification number: H04B17/0085 H04B17/102 H04B17/11 H04B17/18 H04B17/21

    Abstract: One exemplary embodiment of the present invention relates to a circuit that includes at least one RF signal path for an RF signal and at least one power sensor, which is coupled to the RF signal path and configured to generate a sensor signal representing the power of the RF signal during normal operation of the circuit. The circuit further includes a circuit node for receiving an RF test signal during calibration operation of the circuit. The circuit node is coupled to the at least one power sensor, so that the at least one power sensor receives the RF test signal additionally or alternatively to the RF signal and generates the sensor signal as representing the power of the RF test signal.

    Abstract translation: 本发明的一个示例性实施例涉及一种电路,其包括用于RF信号的至少一个RF信号路径和至少一个功率传感器,其耦合到RF信号路径并被配置为产生代表 RF信号在电路正常工作期间。 电路还包括用于在电路的校准操作期间接收RF测试信号的电路节点。 所述电路节点耦合到所述至少一个功率传感器,使得所述至少一个功率传感器另外或替代于所述RF信号接收所述RF测试信号,并且生成所述传感器信号以表示所述RF测试信号的功率。

    End-of line phase calibration of radar devices

    公开(公告)号:US12235384B2

    公开(公告)日:2025-02-25

    申请号:US17651331

    申请日:2022-02-16

    Abstract: A method for the use in a radar system is described herein. In accordance with one implementation, the method includes providing a local oscillator signal to a transmit channel of a radar chip. The transmit channel generates an RF output signal based on the local oscillator signal. An internal RF test signal is generated by applying the local oscillator signal to the transmit channel. First and second phase values are determined for a first and a second value of an influence parameter of the radar chip based on internal measurements of the first and second phase values. Third and fourth phase values are determined for the first and second values of the influence parameter, respectively, based on the RF output signal. A calibration parameter is calculated based on the first, second, third, and fourth phase values and is used to estimate a phase of the RF output signal.

    Phase, phase noise, and slave mode measurement for millimeter wave integrated circuits on automatic test equipment

    公开(公告)号:US11579280B2

    公开(公告)日:2023-02-14

    申请号:US16711928

    申请日:2019-12-12

    Abstract: A radar monolithic microwave integrated circuit (MMIC) includes a first transmission channel configured to output a first continuous-wave transmit signal based on a local oscillator signal having a first frequency; a first phase shifter provided on the first transmission channel and configured to apply a first phase setting to the first continuous-wave transmit signal to generate a first transmit signal having the first frequency; a first transmit monitoring signal path configured to couple out a portion of the first transmit signal from the first transmission channel as a first transmit monitoring signal; a frequency multiplier configured to receive a test signal and convert it into a multiplied test signal having a second frequency, where the first and the second frequencies are separated by a frequency offset; and a down-conversion mixer configured to mix the multiplied test signal and the first transmit monitoring signal to generate a first mixer output signal.

    Oscillator circuit
    9.
    发明授权
    Oscillator circuit 有权
    振荡电路

    公开(公告)号:US09496824B2

    公开(公告)日:2016-11-15

    申请号:US14861054

    申请日:2015-09-22

    Abstract: The disclosure provides an oscillator circuit for a voltage controlled oscillator. The oscillator circuit includes first and second coupled transmission lines, wherein the oscillator circuit is configured to provide a variable load impedance at a first end of a signal line of the first transmission line such that a variable inductance is provided between first and second ends of a signal line of the second transmission line in dependence on the variable load impedance. The oscillator circuit is configured to adjust the variable inductance provided between the first and second ends of the signal line of the second transmission line by adjusting the variable load impedance provided at the first end of the signal line of the first transmission line, wherein the variable inductance provided between the first and second ends of the signal line of the second transmission line constitutes a frequency determining element of the oscillator circuit.

    Abstract translation: 本公开提供了一种用于压控振荡器的振荡器电路。 振荡器电路包括第一和第二耦合传输线,其中振荡器电路被配置为在第一传输线的信号线的第一端处提供可变负载阻抗,使得可变电感被提供在第一和第二端之间 根据可变负载阻抗,第二传输线的信号线。 振荡器电路被配置为通过调节设置在第一传输线的信号线的第一端处的可变负载阻抗来调节设置在第二传输线的信号线的第一和第二端之间的可变电感,其中变量 设置在第二传输线的信号线的第一和第二端之间的电感构成振荡器电路的频率确定元件。

    Systems and Methods for Cascading Radar Chips Having a Low Leakage Buffer
    10.
    发明申请
    Systems and Methods for Cascading Radar Chips Having a Low Leakage Buffer 有权
    具有低泄漏缓冲器的级联雷达芯片的系统和方法

    公开(公告)号:US20160245898A1

    公开(公告)日:2016-08-25

    申请号:US14630754

    申请日:2015-02-25

    CPC classification number: G01S7/032 G01S13/931

    Abstract: A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

    Abstract translation: 公开了级联雷达传感器装置。 该装置包括第一缓冲器和第二缓冲器。 第一缓冲器在第一雷达芯片内并且包括开关,并且被配置为在禁用模式下减轻第一泄漏信号。 第二个缓冲器位于第二个雷达芯片内,并具有禁用模式。 第二个雷达芯片与第一个雷达芯片级联。 控制单元耦合到第一雷达芯片和第二雷达芯片,并且被配置为设置用于第一缓冲器的禁用模式。

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