Invention Application
- Patent Title: Layout Decomposition Methods and Systems
- Patent Title (中): 布局分解方法与系统
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Application No.: US15135041Application Date: 2016-04-21
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Publication No.: US20160313638A1Publication Date: 2016-10-27
- Inventor: Ji-Young Jung , Dae-Kwon KANG , Dong-Gyun KIM , Jae-Seok YANG , Sung-Wook HWANG
- Applicant: Samsung Electronics Co., Ltd.
- Priority: KR10-2015-0058010 20150424
- Main IPC: G03F1/70
- IPC: G03F1/70 ; G06F17/50

Abstract:
A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.
Public/Granted literature
- US09874810B2 Layout decomposition methods and systems Public/Granted day:2018-01-23
Information query
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