公开(公告)号：US20180096935A1

公开(公告)日：2018-04-05

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20210098377A1

公开(公告)日：2021-04-01

申请号：US17120616

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20160313638A1

公开(公告)日：2016-10-27

申请号：US15135041

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Jung ,  Dae-Kwon KANG ,  Dong-Gyun KIM ,  Jae-Seok YANG ,  Sung-Wook HWANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F1/68

Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

Abstract translation: 提供了一种布局分解方法，其可以包括建筑物，包括多个节点和边缘的图形，所述布局设计包括多个多边形，其中所述节点对应于所述布局设计的所述多边形，并且所述边缘标识靠近 彼此距离多个节点之间的距离小于最小距离，将所述多个节点的度数与参考值进行比较，选择目标节点，其程度超过所述参考值，基于所述参考值识别第一和第二子图，基于 目标节点，在第一和第二子图上执行多图案化技术分解以获取第一和第二结果，以及创建对应于布局设计的一部分的第一掩模布局数据和对应于布局设计的另一部分的第二掩模布局数据 结合第一和​​第二结果的布局设计。

公开(公告)号：US20190122988A1

公开(公告)日：2019-04-25

申请号：US16217220

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin KIM ,  Chang-Hwa KIM ,  Hwi-Chan JUN ,  Chul-Hong PARK ,  Jae-Seok YANG ,  Kwan-Young CHUN

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US20180157781A1

公开(公告)日：2018-06-07

申请号：US15701971

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Chul-Hong PARK ,  Jae-Seok YANG

IPC: G06F17/50 ,  H01L21/768 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.

公开(公告)号：US20160026744A1

公开(公告)日：2016-01-28

申请号：US14674416

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Gyun KIM ,  Sung-Wook HWANG ,  Dae-Kwon KANG ,  Jae-Seok YANG ,  Ji-Young JUNG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/3086 ,  H01L27/0207

Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Abstract translation: 布局设计方法可以包括接收与在第一方向上延伸并在垂直于第一方向的第二方向并行布置的第一至第三正常翅片设计相关的预定值，基于预定值产生虚拟翅片设计，产生心轴候选设计 基于第一至第三正常翅片设计和虚拟翅片设计，将心轴候选设计分解为第一和第二心轴掩模设计，以及使用满足预定条件的第一和第二心轴掩模设计中的一个产生最终心轴掩模设计 。 在第一正常翅片设计和第二正常翅片设计之间的第二方向上的第一间隔距离可以不同于第二正常翅片设计和第三正常翅片设计之间的第二方向上的第二间隔距离。