Invention Application
- Patent Title: GROUP III-N NANOWIRE TRANSISTORS
-
Application No.: US15197615Application Date: 2016-06-29
-
Publication No.: US20160315153A1Publication Date: 2016-10-27
- Inventor: Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
- Applicant: Intel Corporation
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/06 ; H01L29/20 ; H01L27/06 ; H01L29/786 ; H01L29/423 ; H01L29/66 ; H01L23/66 ; H01L29/04 ; H01L29/205

Abstract:
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
Public/Granted literature
- US09691857B2 Group III-N nanowire transistors Public/Granted day:2017-06-27
Information query
IPC分类: