公开(公告)号：US20240304543A1

公开(公告)日：2024-09-12

申请号：US18668038

申请日：2024-05-17

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20240222428A1

公开(公告)日：2024-07-04

申请号：US18091206

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Kevin O'Brien ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Sudarat Lee ,  Ande Kitamura ,  Scott B. Clendenning ,  Mahmut Sami Kavrik

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/22 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/22 ,  H01L29/778 ,  H01L29/78696

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

公开(公告)号：US20240170394A1

公开(公告)日：2024-05-23

申请号：US17992818

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  June Choi ,  Manish Chandhok ,  Miriam Reshotko ,  Matthew Metz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53257

Abstract: Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.

公开(公告)号：US11955560B2

公开(公告)日：2024-04-09

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/66 ,  H01L27/22 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20230197643A1

公开(公告)日：2023-06-22

申请号：US17560062

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Sou-Chi Chang ,  Scott Clendenning ,  Matthew Metz

IPC: H01L23/64 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/642 ,  H01L21/0228 ,  H01L23/5286

Abstract: IC die and/or IC die packages including capacitors with a pyrochlore-based insulator material. The pyrochlore-based insulator material comprises a compound of a species A and a species B, each comprising one or more rare earths or metals. In the pyrochlore-based insulator material, oxygen content is advantageously more than three times and less than four times the amount of either of species A or B with crystalline pyrochlore phases having the composition A2B2O7. Within a capacitor, the pyrochlore-based insulator may be amorphous and/or may have one or more crystalline phases. The pyrochlore-based insulator has an exceedingly high relative permittivity of 50-100, or more. The pyrochlore-based insulator material may be deposited at low temperatures compatible with interconnect metallization processes practiced in IC die manufacture as well as IC die packaging.

公开(公告)号：US11616130B2

公开(公告)日：2023-03-28

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

公开(公告)号：US11257904B2

公开(公告)日：2022-02-22

申请号：US16024706

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20210408291A1

公开(公告)日：2021-12-30

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US10784170B2

公开(公告)日：2020-09-22

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: H01L21/84 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/205

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US10186581B2

公开(公告)日：2019-01-22

申请号：US15623165

申请日：2017-06-14

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/04 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L23/66 ,  H01L27/06 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.