发明申请
US20160329911A1 LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION
有权
具有多项式减少功能的低功耗部分并行CHIEN搜索架构
- 专利标题: LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION
- 专利标题(中): 具有多项式减少功能的低功耗部分并行CHIEN搜索架构
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申请号: US14706767申请日: 2015-05-07
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公开(公告)号: US20160329911A1公开(公告)日: 2016-11-10
- 发明人: XINMIAO ZHANG , ITAI DROR
- 申请人: SANDISK TECHNOLOGIES INC.
- 专利权人: SANDISK TECHNOLOGIES INC.
- 当前专利权人: SANDISK TECHNOLOGIES INC.
- 主分类号: H03M13/15
- IPC分类号: H03M13/15
摘要:
A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
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