发明申请
US20160329911A1 LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION 有权
具有多项式减少功能的低功耗部分并行CHIEN搜索架构

LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION
摘要:
A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
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