发明申请
US20160350473A1 Layout Optimization for Integrated Circuit Design 有权
集成电路设计布局优化

Layout Optimization for Integrated Circuit Design
摘要:
A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
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