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公开(公告)号：US09754073B2
公开(公告)日：2017-09-05
申请号：US15237286
申请日：2016-08-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
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公开(公告)号：US09543193B2
公开(公告)日：2017-01-10
申请号：US14833949
申请日：2015-08-24
发明人： Lee-Chung Lu , Yuan-Te Hou , Shyue-Shyh Lin , Li-Chun Tien , Dian-Hau Chen
IPC分类号： H01L23/00 , H01L21/768 , H01L21/311 , H01L23/528 , H01L23/522
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76877 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.
摘要翻译： 集成电路结构包括半导体衬底和半导体衬底上的第一金属层。 第一金属层具有第一最小间距。 第二金属层在第一金属层之上。 第二金属层具有小于第一最小间距的第二最小间距。
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公开(公告)号：US09064081B1
公开(公告)日：2015-06-23
申请号：US14103558
申请日：2013-12-11
发明人： Meng-Kai Hsu , Chi-Yeh Yu , Yuan-Te Hou , Wen-Hao Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.
摘要翻译： 提供了一种线路布线方法。 该方法包括获得单元格布局的数据，生成单元布局的第一数据库，为第一数据库中的每个单元识别第一数据库中的单元和另一单元是否在引脚层中可路由，以及生成第二数据库 对于可路由的单元。
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公开(公告)号：US08898600B2
公开(公告)日：2014-11-25
申请号：US13941941
申请日：2013-07-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译： 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。
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公开(公告)号：US20240086613A1
公开(公告)日：2024-03-14
申请号：US18516499
申请日：2023-11-21
发明人： Yuan-Te Hou , Min-Yuan Tsai
IPC分类号： G06F30/398 , G06F30/31 , G06F30/392
CPC分类号： G06F30/398 , G06F30/31 , G06F30/392
摘要： Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.
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公开(公告)号：US20160350473A1
公开(公告)日：2016-12-01
申请号：US15237286
申请日：2016-08-15
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
摘要翻译： 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。
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公开(公告)号：US20150364359A1
公开(公告)日：2015-12-17
申请号：US14833949
申请日：2015-08-24
发明人： Lee-Chung Lu , Yuan-Te Hou , Shyue-Shyh Lin , Li-Chun Tien , Dian-Hau Chen
IPC分类号： H01L21/768 , H01L23/528 , H01L21/311
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76877 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.
摘要翻译： 集成电路结构包括半导体衬底和半导体衬底上的第一金属层。 第一金属层具有第一最小间距。 第二金属层在第一金属层之上。 第二金属层具有小于第一最小间距的第二最小间距。
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公开(公告)号：US20150199469A1
公开(公告)日：2015-07-16
申请号：US14598773
申请日：2015-01-16
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
摘要翻译： 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。
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9.发明授权Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed 有权形成包括具有不同阈值电压的单元的布局的方法，形成的实现系统和布局公开(公告)号：US08826212B2
公开(公告)日：2014-09-02
申请号：US13793515
申请日：2013-03-11
发明人： Sung-Yen Yeh , Yeh-Chi Chang , Yen-Pin Chen , Zhe-Wei Jiang , King-Ho Tam , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.
摘要翻译： 一种包括开发电路示意图的方法，该电路示意图包括多个单元。 该方法还包括基于电路原理图为多个单元生成单元布置规则，并且基于单元布局规则开发多个单元的电路布局图。 该方法还包括基于阈值电压对电路布局图的多个单元进行分组，并将阈值电压兼容填充器插入到电路布局图中。 描述用于实现该方法的系统。 还描述了由该方法形成的布局。
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10.发明授权公开(公告)号：US10055531B2
公开(公告)日：2018-08-21
申请号：US14622009
申请日：2015-02-13
发明人： Chung-Hsing Wang , King-Ho Tam , Yuan-Te Hou , Chin-Chang Hsu , Meng-Kai Hsu
IPC分类号： G06F17/50 , H01L27/02 , H01L27/11582
CPC分类号： G06F17/5081 , H01L27/0207 , H01L27/11582 , H01L28/00
摘要： In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.
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