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    Layout Optimization for Integrated Circuit Design
    2.
    发明申请
    Layout Optimization for Integrated Circuit Design 有权
    集成电路设计布局优化

    公开(公告)号：US20160350473A1

    公开(公告)日：2016-12-01

    申请号：US15237286

    申请日：2016-08-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

    Abstract translation: 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。

    LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN
    3.
    发明申请
    LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN 有权
    集成电路设计的布局优化

    公开(公告)号：US20150199469A1

    公开(公告)日：2015-07-16

    申请号：US14598773

    申请日：2015-01-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

    Abstract translation: 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。

    Layout optimization for integrated circuit design
    4.
    发明授权
    Layout optimization for integrated circuit design 有权
    集成电路设计布局优化

    公开(公告)号：US09418196B2

    公开(公告)日：2016-08-16

    申请号：US14598773

    申请日：2015-01-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50 ,  G03F7/00

    CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

    Abstract translation: 一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束 模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或 在检查期间发现第二个约束。

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