Invention Application
US20160351661A1 PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT
审中-公开
用于生产具有来自SOI和特定FDSOI衬底的较大通道宽度的MOS晶体管的工艺以及相应的集成电路
- Patent Title: PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT
- Patent Title (中): 用于生产具有来自SOI和特定FDSOI衬底的较大通道宽度的MOS晶体管的工艺以及相应的集成电路
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Application No.: US14962193Application Date: 2015-12-08
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Publication No.: US20160351661A1Publication Date: 2016-12-01
- Inventor: Stephane Monfray , Thomas Skotnicki
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Priority: FR1554755 20150527
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L21/02 ; H01L29/66 ; H01L29/165 ; H01L29/423 ; H01L21/762
Abstract:
An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone. The concave semiconductor region contains drain, source and channel regions. A gate region for the transistor possesses a concave portion overlapping a portion of the concave semiconductor region. A dielectric region is located between the zone of the substrate and the concave semiconductor region.
Information query
IPC分类:
