Invention Application
US20170024145A1 ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM
审中-公开
地址转换和数据缓存在缓存存储器系统中
- Patent Title: ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM
- Patent Title (中): 地址转换和数据缓存在缓存存储器系统中
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Application No.: US14807754Application Date: 2015-07-23
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Publication No.: US20170024145A1Publication Date: 2017-01-26
- Inventor: TAREK ZGHAL , Alain Dominique Artieri , Jason Edward Podaima , Meghal Varia , Serag GadelRab
- Applicant: QUALCOMM INCORPORATED
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/08

Abstract:
Systems, methods, and computer program products are disclosed for reducing latency in a system that includes one or more processing devices, a system memory, and a cache memory. A pre-fetch command that identifies requested data is received from a requestor device. The requested data is pre-fetched from the system memory into the cache memory in response to the pre-fetch command. The data pre-fetch may be preceded by a pre-fetch of an address translation. A data access request corresponding to the pre-fetch command is then received, and in response to the data access request the data is provided from the cache memory to the requestor device.
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