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    ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM
    2.
    发明申请
    ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM 审中-公开
    地址转换和数据缓存在缓存存储器系统中

    公开(公告)号：US20170024145A1

    公开(公告)日：2017-01-26

    申请号：US14807754

    申请日：2015-07-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： TAREK ZGHAL ,  Alain Dominique Artieri ,  Jason Edward Podaima ,  Meghal Varia ,  Serag GadelRab

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

    Abstract: Systems, methods, and computer program products are disclosed for reducing latency in a system that includes one or more processing devices, a system memory, and a cache memory. A pre-fetch command that identifies requested data is received from a requestor device. The requested data is pre-fetched from the system memory into the cache memory in response to the pre-fetch command. The data pre-fetch may be preceded by a pre-fetch of an address translation. A data access request corresponding to the pre-fetch command is then received, and in response to the data access request the data is provided from the cache memory to the requestor device.

    Abstract translation: 公开了系统，方法和计算机程序产品，用于减少包括一个或多个处理设备，系统存储器和高速缓冲存储器的系统中的延迟。 从请求器设备接收到识别所请求数据的预取命令。 响应于预取命令，将所请求的数据从系统存储器预取入高速缓冲存储器。 之前的数据预取可以预先获取地址转换。 然后接收与预取命令相对应的数据访问请求，并且响应于数据访问请求，将数据从高速缓冲存储器提供给请求器设备。

    POWER MULTIPLEXER FOR INTEGRATED CIRCUIT POWER GRID EFFICIENCY
    3.
    发明申请
    POWER MULTIPLEXER FOR INTEGRATED CIRCUIT POWER GRID EFFICIENCY 有权
    集成电路功率多路复用器功率因数

    公开(公告)号：US20170060224A1

    公开(公告)日：2017-03-02

    申请号：US14836694

    申请日：2015-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Tauseef Kazi ,  Alain Dominique Artieri

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203

    Abstract: An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

    Abstract translation: 集成电路设置有低功率岛，其包括嵌入式存储器电力域，其可以选择性地耦合到在第一电力轨上提供的有源模式电源电压或提供在第二电力轨上的睡眠模式电源电压 。

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