公开(公告)号：US10609418B2

公开(公告)日：2020-03-31

申请号：US15490620

申请日：2017-04-18

Applicant: QUALCOMM INCORPORATED

Inventor： Serag Gadelrab ,  Chinchuan Chiu ,  Moinul Khan ,  Kyle Ernewein ,  Tom Longo ,  Simon Booth ,  Meghal Varia ,  Milivoje Aleksic

IPC: H04N19/85 ,  H04N19/103 ,  H04N19/176 ,  H04N19/156 ,  H04N19/172 ,  H04N19/146 ,  H04N19/152 ,  H04N19/117

Abstract: An exemplary method for intelligent compression defines a threshold value for a temperature reading generated by a temperature sensor. Data blocks received into the compression module are compressed according to either a first mode or a second mode, the selection of which is determined based on a comparison of the active level for the temperature reading to the defined threshold value. The first compression mode may be associated with a lossless compression algorithm while the second compression mode is associated with a lossy compression algorithm. Or, both the first compression mode and the second compression mode may be associated with a lossless compression algorithm, however, for the first compression mode the received data blocks are produced at a default high quality level setting while for the second compression mode the received data blocks are produced at a reduced quality level setting.

公开(公告)号：US10037280B2

公开(公告)日：2018-07-31

申请号：US14726454

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab ,  Muhammad Umar Choudry

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0862 ,  G06F12/109

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

公开(公告)号：US10019380B2

公开(公告)日：2018-07-10

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/00 ,  G06F12/1072 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US20170091116A1

公开(公告)日：2017-03-30

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/10

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US11006127B2

公开(公告)日：2021-05-11

申请号：US16588818

申请日：2019-09-30

Applicant: QUALCOMM INCORPORATED

Inventor： Meghal Varia ,  Serag Gadelrab ,  Wesley James Holland ,  Joseph Cheung ,  Dam Backer ,  Tom Longo

IPC: H04N19/162 ,  H04N19/167 ,  H04N19/174 ,  H04N19/115 ,  H04N19/119 ,  G06F12/02 ,  H04N19/12 ,  H04N19/172 ,  H04N19/46 ,  H04N5/917

Abstract: An exemplary method for intelligent compression uses a foveated-compression approach. First, the location of a fixation point within an image frame is determined. Next, the image frame is sectored into two or more sectors such that one of the two or more sectors is designated as a fixation sector and the remaining sectors are designated as foveation sectors. A sector may be defined by one or more tiles within the image frame. The fixation sector includes the particular tile that contains the fixation point and is compressed according to a lossless compression algorithm. The foveation sectors are compressed according to lossy compression algorithms. As the locations of foveation sectors increase in angular distance from the location of the fixation sector, a compression factor may be increased.

公开(公告)号：US10509588B2

公开(公告)日：2019-12-17

申请号：US14995125

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Serag Gadelrab ,  Sudeep Ravi Kottilingal ,  Meghal Varia ,  Pooja Sinha ,  Ujwal Patel ,  Ruo Long Liu ,  Jeffrey Chu ,  Sina Gholamian ,  Hyukjune Chung ,  David Strasser ,  Raghavendra Nagaraj ,  Eric Demers

IPC: G06F3/06 ,  G06F13/16 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234

Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.

公开(公告)号：US20180253236A1

公开(公告)日：2018-09-06

申请号：US15448095

申请日：2017-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： SERAG GADELRAB ,  Jason Edward Podaima ,  Kyle Ernewein ,  Meghal Varia

IPC: G06F3/06 ,  G06F12/1009 ,  G06F9/50

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/5016 ,  G06F12/1009 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1689 ,  G06F2212/1024

Abstract: A method and system for dynamic control of shared memory resources within a portable computing device (“PCD”) are disclosed. A limit request of an unacceptable deadline miss (“UDM”) engine of the portable computing device may be determined with a limit request sensor within the UDM element. Next, a memory management unit modifies a shared memory resource arbitration policy in view of the limit request. By modifying the shared memory resource arbitration policy, the memory management unit may smartly allocate resources to service translation requests separately queued based on having emanated from either a flooding engine or a non-flooding engine.

公开(公告)号：US09792215B2

公开(公告)日：2017-10-17

申请号：US14672133

申请日：2015-03-28

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab

IPC: G06F12/12 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028 ,  G06F2212/654 ,  G06F2212/684

Abstract: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.

公开(公告)号：US12182676B2

公开(公告)日：2024-12-31

申请号：US18539022

申请日：2023-12-13

Applicant: QUALCOMM Incorporated

Inventor： Serag Gadelrab ,  James Esliger ,  Meghal Varia ,  Kyle Ernewein ,  Alwyn Dos Remedios ,  George Lee

IPC: G06N20/00 ,  G06F11/34 ,  G06N5/04

Abstract: Certain aspects of the present disclosure provide techniques for concurrently performing inferences using a machine learning model and optimizing parameters used in executing the machine learning model. An example method generally includes receiving a request to perform inferences on a data set using the machine learning model and performance metric targets for performance of the inferences. At least a first inference is performed on the data set using the machine learning model to meet a latency specified for generation of the first inference from receipt of the request. While performing the at least the first inference, operational parameters resulting in inference performance approaching the performance metric targets are identified based on the machine learning model and operational properties of the computing device. The identified operational parameters are applied to performance of subsequent inferences using the machine learning model.

公开(公告)号：US11556798B2

公开(公告)日：2023-01-17

申请号：US16905541

申请日：2020-06-18

Applicant: QUALCOMM Incorporated

Inventor： Meghal Varia

IPC: G06N3/08 ,  G06N5/04

Abstract: Certain aspects of the present disclosure provide techniques for receiving data defining a neural network; analyzing the data to determine a depth-first cut point for a depth-first traversal portion of an overall network traversal; performing depth-first traversal for the depth-first portion of the overall network traversal; and performing layer-based traversal for a layer-based portion of the overall network traversal.