发明申请
US20170047333A1 DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME
审中-公开
具有通过（ILV）的层间隔的装置及其制造方法
- 专利标题： DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME
- 专利标题（中）： 具有通过（ILV）的层间隔的装置及其制造方法
-
申请号： US15333439申请日： 2016-10-25
-
公开(公告)号： US20170047333A1公开(公告)日： 2017-02-16
- 发明人: Tsung-Hsien HUANG , Hong-Chen CHENG , Cheng Hung LEE , Hung-Jen LIAO
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 主分类号： H01L27/112
- IPC分类号： H01L27/112 ; H01L23/528 ; H01L21/768 ; H01L23/522
摘要：
A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.
公开/授权文献
信息查询
IPC分类:
