公开(公告)号：US20190096895A1

公开(公告)日：2019-03-28

申请号：US16205751

申请日：2018-11-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Hong-Chen CHENG ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC分类号： H01L27/112 ,  G11C7/18

摘要： A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.

公开(公告)号：US20230326505A1

公开(公告)日：2023-10-12

申请号：US18336418

申请日：2023-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Wei-Jer HSIEH ,  Yu-Hao HSU

IPC分类号： G11C8/18 ,  H03K19/017 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08

CPC分类号： G11C8/18 ,  H03K19/01742 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08 ,  G11C7/12

摘要： A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.

公开(公告)号：US20150091098A1

公开(公告)日：2015-04-02

申请号：US14039481

申请日：2013-09-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Hong-Chen CHENG ,  Cheng-Hung LEE ,  Hung-Jen LIAO

IPC分类号： H01L27/112 ,  H01L23/522

CPC分类号： H01L27/1128 ,  G11C7/18 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device.

摘要翻译： 三维半导体器件包括第一存储器件，第二存储器件和通孔。 通孔将第一存储器件连接到第二存储器件。

公开(公告)号：US20170047333A1

公开(公告)日：2017-02-16

申请号：US15333439

申请日：2016-10-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Hong-Chen CHENG ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC分类号： H01L27/112 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L27/1128 ,  G11C7/18 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.

摘要翻译： 三维集成电路包括第一晶体管，字线，第一通孔，第二晶体管和第二通孔。 第一晶体管处于第一电平，第二晶体管处于第二电平。 第二级与第一级不同。 字线和第一通孔耦合到第一晶体管。 第二通孔耦合在第一晶体管和第二晶体管之间。

公开(公告)号：US20230064595A1

公开(公告)日：2023-03-02

申请号：US17459624

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Wei-Jer HSIEH ,  Yu-Hao HSU

IPC分类号： G11C11/408 ,  G11C11/4076 ,  G11C11/4094 ,  H03K19/017

摘要： A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.

公开(公告)号：US20210272968A1

公开(公告)日：2021-09-02

申请号：US17325708

申请日：2021-05-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Hong-Chen CHENG ,  Hung-Jen LIAO ,  Cheng Hung LEE

IPC分类号： H01L27/112 ,  H01L23/522 ,  G11C7/18 ,  H01L21/768 ,  H01L23/528

摘要： A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.