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    LATCH TYPE SENSE AMPLIFIER
    2.
    发明申请
    LATCH TYPE SENSE AMPLIFIER 有权

    公开(公告)号：US20230064056A1

    公开(公告)日：2023-03-02

    申请号：US17461216

    申请日：2021-08-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hua-Hsin YU ,  Hung-Jen LIAO ,  Cheng-Hung LEE ,  Hau-Tai SHIEH

    IPC: G11C7/06

    Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT 有权

    公开(公告)号：US20220366965A1

    公开(公告)日：2022-11-17

    申请号：US17816048

    申请日：2022-07-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Li-Wen WANG ,  Jonathan Tsung-Yung CHANG ,  Yen-Huei CHEN

    IPC: G11C11/4094 ,  G11C7/12 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/419 ,  H01L21/48 ,  H01L27/11

    Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

    MEMORY COMPUTATION CIRCUIT
    4.
    发明申请
    MEMORY COMPUTATION CIRCUIT 有权

    公开(公告)号：US20220328096A1

    公开(公告)日：2022-10-13

    申请号：US17808536

    申请日：2022-06-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yen-Huei CHEN ,  Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: G11C11/419 ,  G11C11/412 ,  G06N3/08 ,  G06F17/16

    Abstract: A memory circuit includes a first memory array including first memory cells wherein a plurality of first word lines is coupled with a plurality of rows of first memory cells in a first segment of the first memory array, and a plurality of second word lines is coupled with the plurality of rows of first memory cells in a second segment of the first memory array. The memory circuit also includes a read circuit configured to retrieve data from the first memory cells of the first memory array and a computation circuit configured to perform a matrix computation by combining first data retrieved from the first memory cells of the first segment with second data retrieved from the first memory cells of the second segment.

    MEMORY CIRCUIT HAVING SHARED WORD LINE
    7.
    发明申请
    MEMORY CIRCUIT HAVING SHARED WORD LINE 审中-公开
    具有共享字线的存储器电路

    公开(公告)号：US20160372181A1

    公开(公告)日：2016-12-22

    申请号：US15251260

    申请日：2016-08-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hidehiro FUJIWARA ,  Li-Wen WANG ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C11/418 ,  H01L27/0207 ,  H01L27/1116

    Abstract: A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.

    Abstract translation: 存储电路包括第一和第二存储单元。 第一存储器单元具有具有通孔的访问端口。 第二存储单元还具有具有通孔的访问端口。 第一和第二存储器单元沿列方向彼此邻接。 电路包括在第一和第二存储器单元上的至少一个导电结构。 导电结构可以是两个互连的导电线。 导电结构在导电层中沿着行方向延伸并且电耦合到通孔的栅极端子。

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