Invention Application
US20170060218A1 SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS
有权
用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER
- Patent Title: SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS
- Patent Title (中): 用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER
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Application No.: US15302767Application Date: 2014-05-21
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Publication No.: US20170060218A1Publication Date: 2017-03-02
- Inventor: Le Zhang , Wenjun Su , Chulkyu Lee
- Applicant: Wenjen SU , Le ZHANG , Chulkyu LEE , QUALCOMM Incorporated
- International Application: PCT/CN2014/077979 WO 20140521
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F13/42 ; G06F1/08 ; G06F13/40 ; H03M9/00 ; G11C19/28

Abstract:
Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
Public/Granted literature
- US10007320B2 Serializer and deserializer for odd ratio parallel data bus Public/Granted day:2018-06-26
Information query