Invention Application
US20170060218A1 SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS 有权
用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER

SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS
Abstract:
Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
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