Invention Application
US20170068772A1 SYSTEM FOR OPTIMIZING POWER LEAKAGE AND TIMING DELAY IN AN INTEGRATED CIRCUIT BASED ON A COST FACTOR OF REPLACING CELLS
审中-公开
基于替代细胞的成本因素优化集成电路中的功率泄漏和定时延迟的系统
- Patent Title: SYSTEM FOR OPTIMIZING POWER LEAKAGE AND TIMING DELAY IN AN INTEGRATED CIRCUIT BASED ON A COST FACTOR OF REPLACING CELLS
- Patent Title (中): 基于替代细胞的成本因素优化集成电路中的功率泄漏和定时延迟的系统
-
Application No.: US15258923Application Date: 2016-09-07
-
Publication No.: US20170068772A1Publication Date: 2017-03-09
- Inventor: Kelageri NAGARAJ , Paras GUPTA , Thomas YU , Venkatesh NAYAK , Anil Kumar KODURU , Bhanuprakash GANGULA VENKATARAMA REDDY
- Applicant: QUALCOMM Incorporated
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K5/13 ; H03K19/00
Abstract:
A method of and an apparatus for optimizing timing delay and power leakage in a circuit. The apparatus determines at least one path of a plurality of paths in a network of logic elements, the at least one path including a plurality of cells, each of the cells being configured to perform a logical operation. In addition, the apparatus identifies a first cell of the plurality of cells based on a first cost factor associated with replacing the first cell with a first replacement cell that performs the same logical operation, the first cost factor being a function of a power leakage difference and a timing delay difference associated with the first cell and the first replacement cell. Furthermore, the apparatus replaces the first cell with the first replacement cell in the at least one path.
Information query
