公开(公告)号：US20170068772A1

公开(公告)日：2017-03-09

申请号：US15258923

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Kelageri NAGARAJ ,  Paras GUPTA ,  Thomas YU ,  Venkatesh NAYAK ,  Anil Kumar KODURU ,  Bhanuprakash GANGULA VENKATARAMA REDDY

IPC: G06F17/50 ,  H03K5/13 ,  H03K19/00

CPC classification number: G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H03K5/13 ,  H03K19/0008 ,  H03K2005/00019

Abstract: A method of and an apparatus for optimizing timing delay and power leakage in a circuit. The apparatus determines at least one path of a plurality of paths in a network of logic elements, the at least one path including a plurality of cells, each of the cells being configured to perform a logical operation. In addition, the apparatus identifies a first cell of the plurality of cells based on a first cost factor associated with replacing the first cell with a first replacement cell that performs the same logical operation, the first cost factor being a function of a power leakage difference and a timing delay difference associated with the first cell and the first replacement cell. Furthermore, the apparatus replaces the first cell with the first replacement cell in the at least one path.

Abstract translation: 一种用于优化电路中的定时延迟和功率泄漏的方法和装置。 所述装置确定逻辑元件的网络中的多个路径的至少一个路径，所述至少一个路径包括多个小区，每个小区被配置为执行逻辑运算。 此外，该装置基于与执行相同逻辑运算的第一替换单元替换第一单元相关联的第一成本因素来识别多个单元中的第一单元，第一成本因子是功率泄漏差的函数 以及与第一小区和第一替换小区相关联的定时延迟差异。 此外，装置用至少一个路径中的第一替换单元替换第一单元。