Invention Application
US20170069725A1 NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
审中-公开
具有掺杂亚区域的OMEGA-FIN的非平面半导体器件及其制造方法
- Patent Title: NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
- Patent Title (中): 具有掺杂亚区域的OMEGA-FIN的非平面半导体器件及其制造方法
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Application No.: US15122796Application Date: 2014-06-26
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Publication No.: US20170069725A1Publication Date: 2017-03-09
- Inventor: GOPINATH BHIMARASETTI , WALID M. HAFEZ , JOODONG PARK , WEIMIN HAN , RAYMOND E. COTNER , CHIA-HONG JAN
- Applicant: Intel Corporation
- International Application: PCT/US2014/044433 WO 20140626
- Main IPC: H01L29/36
- IPC: H01L29/36 ; H01L21/8234 ; H01L29/66 ; H01L27/088

Abstract:
Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
Public/Granted literature
- US10355093B2 Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same Public/Granted day:2019-07-16
Information query
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